Question E6C06:
Why do CMOS digital integrated circuits have high immunity to noise on the input signal or power supply?  

Choices:  
A: Large bypass capacitance is inherent  
B: The input switching threshold is about twice the power supply voltage  
C: The input switching threshold is about half the power supply voltage  
D: Bandwidth is very limited    

Correct Answer is  C: The input switching threshold is about half the power supply voltage  

CMOS inputs switch near mid-supply, so small noise riding on a valid logic level won’t push it across the decision point.

Why the correct answer (C) is correct
- A CMOS inverter’s switching threshold (trip point) is approximately half the supply:  
  $$V_M \approx \frac{V_{DD}}{2}$$
- Logic 0 is near 0 V and logic 1 is near $V_{DD}$, so there is a large voltage “gap” from either valid level to the mid-supply threshold.
- Supply noise tends to shift both the logic levels and the threshold together (since $V_M$ tracks $V_{DD}$), preserving noise margin.

Why the other choices are incorrect
- A: Large bypass capacitance is not inherent to CMOS; decoupling capacitors are external components. While decoupling helps, it’s not the fundamental reason.
- B: “About twice the power supply voltage” is impossible—thresholds cannot exceed $V_{DD}$ and, in CMOS, scale with it.
- D: CMOS is not inherently very bandwidth-limited; modern CMOS logic can be very fast. Bandwidth isn’t the primary reason for noise immunity.

Useful formulas and rules of thumb
- CMOS inverter trip point:  
  $$V_M \approx \frac{V_{DD}}{2}$$
- Noise margins (general definitions):  
  $$NM_H = V_{OH(min)} - V_{IH(min)}$$  
  $$NM_L = V_{IL(max)} - V_{OL(max)}$$
- Rule of thumb for many CMOS families:  
  $$V_{IL(max)} \approx 0.3\,V_{DD}, \quad V_{IH(min)} \approx 0.7\,V_{DD}$$  
  This yields large noise margins (each ≈ 0.3 $V_{DD}$). For $V_{DD}=5$ V, each margin is about 1.5 V, illustrating strong noise immunity.