Question E6C03:
What is tri-state logic?  

Choices:  
A: Logic devices with 0, 1, and high-impedance output states  
B: Logic devices that utilize ternary math  
C: Logic with three output impedances which can be selected to better match the load impedance  
D: A counter with eight states    

Correct Answer is  A: Logic devices with 0, 1, and high-impedance output states  

Tri-state logic lets a digital output be in one of three conditions:
- Logic 0 (low)
- Logic 1 (high)
- High-impedance (Hi-Z), which effectively disconnects the output from the circuit

Why A is correct:
- Tri-state outputs add a third state, Hi-Z, controlled by an enable line. In Hi-Z, the output’s effective output impedance is very large ($Z_{out} \to \infty$), so it neither drives the line nor significantly loads it. This allows multiple devices to share a common bus—only one device drives 0 or 1 at a time; others stay in Hi-Z.

Why the others are incorrect:
- B: “Ternary math” means three logic levels as actual data values (e.g., 0/1/2). Tri-state logic still uses binary data (0 or 1); the third state is not a data value but a disconnected output condition.
- C: Tri-state does not provide three selectable output impedances for matching. It provides two low-impedance drive states (0 or 1) and one very high impedance state (Hi-Z). It’s not for impedance matching.
- D: “A counter with eight states” describes a 3-bit binary counter (since $2^3 = 8$), not tri-state logic.

Useful rules of thumb:
- In Hi-Z: output current is near zero ($I \approx 0$), and the pin behaves like it’s disconnected.
- Only one device should actively drive a shared bus at a time to avoid bus contention; others must be in Hi-Z.
- Control pin naming varies: OE (Output Enable), CE (Chip Enable), or EN typically controls entry to Hi-Z.