Question E6C05:
Which of the following digital logic families has the lowest power consumption?  

Choices:  
A: Schottky TTL  
B: ECL  
C: NMOS  
D: CMOS    

Correct Answer is  D: CMOS  

CMOS is correct because complementary MOSFET gates draw almost no DC current except during switching. This makes their average power far lower than bipolar or single-ended MOS families at typical logic speeds.

Why D (CMOS) is correct
- CMOS static power is near zero: $P_{static} \approx V_{DD} \cdot I_{leak}$, with $I_{leak}$ very small.
- Dynamic power dominates and scales with switching: 
  $$P_{dyn} = \alpha\, C_L\, V_{DD}^2\, f$$
  where $\alpha$ is the activity factor, $C_L$ the load capacitance, $V_{DD}$ the supply, and $f$ the frequency.
- Result: exceptionally low average power for low-to-moderate frequencies typical in many ham applications.

Why the other choices are incorrect
- A: Schottky TTL (S-TTL)
  - Bipolar logic with continuous bias currents; Schottky clamps prevent saturation to speed switching, not to minimize power.
  - Static current is significant: $P \approx V_{CC}\, I_{CC}$ even when not switching.
  - Lower power than standard TTL only in “LS” variants, but still far higher than CMOS.

- B: ECL (Emitter-Coupled Logic)
  - Uses a differential pair with essentially constant bias current (no transistor saturation).
  - Very fast but very power-hungry; power is largely independent of switching: $P \approx V \cdot I_{bias}$ per gate, continuously.

- C: NMOS
  - Single-ended MOS with resistive/depletion loads creates a DC path when output is low, so it has static power dissipation.
  - More efficient than bipolar in some cases, but still much higher static power than CMOS.

Useful rules of thumb
- Power ordering (lowest to highest): CMOS ≪ LS-TTL/TTL < NMOS (varies) ≪ ECL.
- General gate power estimates at 5 V:
  - CMOS: near 0 static; dynamic depends on $C V^2 f$ (often μW–low mW per gate at modest f).
  - LS-TTL/TTL: mW per gate (static + dynamic).
  - ECL: tens of mW per gate, even idle.
- Key formulas:
  - $P = V \cdot I$
  - CMOS: $P_{avg} \approx \alpha C_L V_{DD}^2 f + V_{DD} I_{leak}$

Bottom line: CMOS minimizes power because it eliminates DC current paths in steady state; others have continuous bias currents.