*Question E6C05:
Which of the following digital logic families has the lowest power consumption?*  

*Correct Answer is  D: CMOS*  

### AI Response: (may contain errors)  

CMOS (Complementary Metal-Oxide-Semiconductor) is the digital logic family with the lowest power consumption. Here's why:

1. **Why CMOS is Correct:**
   - **Low Power Consumption:** CMOS technology uses complementary and symmetrical pairs of p-type and n-type MOSFETs. The key advantage is that it only consumes significant power during the switching of states (from 0 to 1 or 1 to 0). In a steady state (either 0 or 1), the power consumption is minimal because there is no direct path for current to flow between the power supply and ground.
   - **Power Formula:** The power consumption in CMOS circuits is primarily due to capacitive charging and discharging, given by:
     $$ P = C_L \cdot V_{DD}^2 \cdot f $$
     where:
     - $C_L$ = load capacitance
     - $V_{DD}$ = supply voltage
     - $f$ = frequency of operation

2. **Why Other Choices are Incorrect:**
   - **Schottky TTL (A):** Schottky TTL (Transistor-Transistor Logic) uses Schottky diodes to reduce switching time, but it has higher power consumption compared to CMOS because it draws current continuously, even when not switching.
   - **ECL (B):** Emitter-Coupled Logic (ECL) is known for its high-speed performance but at the cost of very high power consumption. ECL circuits are always in an active state, leading to constant power draw.
   - **NMOS (C):** NMOS logic uses n-type MOSFETs and generally consumes more power than CMOS because it requires a continuous current path to maintain a logic level, leading to higher static power consumption.

In summary, CMOS is the most power-efficient choice due to its low static power consumption, making it ideal for battery-powered and low-power applications.